hardware - SandyBridge: How does physical memory map across channels when interleaving is enabled/disabled? -


i have 2 low-level question how memory interleaving across channels works on sandy bridge processors. i've poured through technical documents intel, , still cannot find answers. can help?

multi-channel memory controllers in modern cpus stripe data across memory channels. allows reads , writes carried out in parallel, increasing performance.

question #1: chunck size sandy bridge uses interleaving? i've found information suggests cache-line size. on other hand, others have suggested configurable (at least in older intel architectures). it? can point intel document?

some cpus allow interleaving disabled. confirmed bios settings of high-end systems such hp's proliant , fujitsu's primergy. closest documentation intel can find on section 4.4.4.3 in e5 product family data sheet. have gone far contacting hp how proliants work when interleaving disabled, on conference call, unable answer question.

question #2: how memory mapped across channels when interleaving disabled? presumably, different spare or mirror mode configurations.


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