serial port - ATMEGA32 UART Communication -

i trying serial communication in atmega32 , have question:

in asynchronous serial communication both ubrrh , ucsrc registers have same location. don't know conditions location act ubrrh , conditions, act ucsrc. need different values each register according work assigned registers

in datasheet, have mentioned use of ursel bit selection betweem 2 registers somehow not getting that.

the answer is: yes, ursel bit. according datasheet:

when doing write access of i/o location, high bit of value written, usart register select (ursel) bit, controls 1 of 2 registers written. if ursel 0 during write operation, ubrrh value updated. if ursel one, ucsrc setting updated.

this means, when write ucsrc, regardless of value want put there, set ursel bit (make sure ursel 1):

ucsrc = (1<<ursel)| ... whatever else ... 

when write ubrrh, make sure ursel bit must zero. here different ways of doing that:

ubrrh = (0<<ursel)| ... whatever else ...  // showing ursel isn't set ubrrh = ...some value...                   // simple not setting ursel ubrrh = (somevalue)&(~(1<<ursel)           // ensuring ursel isn't set 

ursel bit high bit. whatever value write ucsrc, set (turn on, make 1) high bit (bit 7). , when writing ubrrh, make sure bit 7 cleared. way of thinking it, every value write ubrrh must under 128. , every value want write ucsrc, add 128 it: turn on bit 7. way of explanation, code above clearer.

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how done? don't know, not uc designer. seems same io location location mapped 2 different registers in processor. have register named foo, , when write value uc checks if high bit set. if writes value internal memory location 1 , if isn't writes value internal memory location 2.

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if using ursel bit correctly, values being written correctly. testing not showing correct values because not reading them propertly. page 162 of datasheet:

doing read access ubrrh or ucsrc register more complex operation. how- ever, in applications, necessary read of these registers.

the read access controlled timed sequence. reading i/o location once returns ubrrh register contents. if register location read in previous system clock cycle, reading register in current clock cycle return ucsrc contents. note timed sequence reading ucsrc atomic operation. interrupts must therefore controlled (for example disabling interrupts globally) during read operation.

so when read ubrrh / ucsrc first time ubrrh. if immediately read again read ucsrc. documentation suggests, there no real reason read these registers. seems not trust datasheet, mistake: datasheet best source of information such matters: without datasheets nowhere.