My Verilog behavioral code getting simulated properly but not working as expected on FPGA -

i wrote behavioral program booth multiplier(radix 2) using state machine concept,am getting the results during program simulation using modelsim, when port fpga(spartan 3) results not expected. please me this.where have gone wrong?

module booth_using_statemachine(mul_a,mul_b,mul_result,clk,reset);  input mul_a,mul_b,clk,reset; output mul_result; wire [7:0] mul_a,mul_b; reg [7:0] mul_result;   reg [15:0] r_b; reg [7:0] r_a; reg prev; reg [1:0] state; reg [3:0] count;  parameter start=1 ,add=2 ,shift=3; @(state) begin  case(state)    start:    begin       r_a   <= mul_a;       r_b   <= {8'b00000000,mul_b};       prev  <= 1'b0;       count <= 3'b000;       mul_result <= r_b[7:0];      end     add:    begin       case({r_b[0],prev})           2'b00:            begin              prev <= 1'b0;             end           2'b01:            begin              r_b[15:8] <= r_b[15:8] + r_a;          prev      <= 1'b0;             end           2'b10:          begin               r_b[15:8] <= r_b[15:8] - r_a;               prev      <= 1'b1;              end           2'b11:             begin               prev <=1'b1;              end          endcase      end    shift:    begin      r_b  <= {r_b[15],r_b[15:1]};      count <= count + 1;     end  endcase   end       @(posedge clk or posedge reset)   begin     if(reset==1)       state <= start;      else       begin          case(state)              start:               state <= add;              add:               state <= shift;               shift:               begin                   if(count>7)                   state <= start;              else               state <=add;                  end         endcase   end   end     endmodule 

you have incomplete sensitivity list in combinational always block. change:

always @(state) 

to:

always @* 

this may synthesizing latches.

use blocking assignments in combinational always block. change <= =.

good synthesis , linting tools should warn these constructs.