c - Qt atomic operation uses condition code register which isn't present in my MIPS 24k core -


i using mips 24k core doesn't have fpu. have cross compiled qt , works fine. when touches qbasicatomicint::testandsetacquire() defined in qatomic_mips.h , sigsegv.

the body of code has inline assembly language. first time i'm working it. when tried find faulty line @ first, pointed last line mentions list of clobbered registers.

later when took approach, seems fail in line highlighted below. idea _q_value means?

inline bool qbasicatomicint::testandsetacquire(int expectedvalue, int newvalue) { register int result; register int tempvalue; asm volatile(".set push\n"              set_mips2              "0:\n"              "ll %[result], %[_q_value]\n" //this line causes sigsegv              "xor %[result], %[result], %[expectedvalue]\n"              "bnez %[result], 0f\n"              "nop\n"              "move %[tempvalue], %[newvalue]\n"              "sc %[tempvalue], %[_q_value]\n"              "beqz %[tempvalue], 0b\n"              "nop\n"              "sync\n"              "0:\n"              ".set pop\n"              : [result] "=&r" (result),                [tempvalue] "=&r" (tempvalue),                [_q_value] "+m" (_q_value)              : [expectedvalue] "r" (expectedvalue),                [newvalue] "r" (newvalue)              : "cc", "memory");  return result == 0; }

disassembly:

00207478 <_zn20qeventdispatcherunix6wakeupev>: 207478: 3c1c001a    lui gp,0x1a 20747c: 279c99f8    addiu   gp,gp,-26120 207480: 0399e021    addu    gp,gp,t9 207484: 27bdffc8    addiu   sp,sp,-56 207488: afbf0030    sw  ra,48(sp) 20748c: afb3002c    sw  s3,44(sp) 207490: afb20028    sw  s2,40(sp) 207494: afb10024    sw  s1,36(sp) 207498: afb00020    sw  s0,32(sp) 20749c: afbc0010    sw  gp,16(sp) 2074a0: 8c860004    lw  a2,4(a0) 2074a4: 00001821    move    v1,zero 2074a8: 24020001    li  v0,1 2074ac: c0c40768    ll  a0,1896(a2) //this exact line 2074b0: 00832026    xor a0,a0,v1 2074b4: 14800008    bnez    a0,2074d8 <_zn20qeventdispatcherunix6wakeupev+0x60> 2074b8: 00000000    nop 2074bc: 00000000    nop 2074c0: 00402821    move    a1,v0 2074c4: e0c50768    sc  a1,1896(a2) 2074c8: 10a0fff8    beqz    a1,2074ac <_zn20qeventdispatcherunix6wakeupev+0x34> 2074cc: 00000000    nop 2074d0: 00000000    nop 2074d4: 0000000f    sync 2074d8: 14800012    bnez    a0,207524 <_zn20qeventdispatcherunix6wakeupev+0xac> 2074dc: 27b30018    addiu   s3,sp,24 2074e0: a3a00018    sb  zero,24(sp) 2074e4: 8cd00058    lw  s0,88(a2) 2074e8: 2412ffff    li  s2,-1 2074ec: 24110004    li  s1,4 2074f0: 8f99cef0    lw  t9,-12560(gp) 2074f4: 02002021    move    a0,s0 2074f8: 02602821    move    a1,s3 2074fc: 0320f809    jalr    t9 207500: 24060001    li  a2,1 207504: 8fbc0010    lw  gp,16(sp) 207508: 14520006    bne v0,s2,207524    <_zn20qeventdispatcherunix6wakeupev+0xac> 20750c: 8f99c864    lw  t9,-14236(gp) 207510: 0320f809    jalr    t9 207514: 00000000    nop 207518: 8c430000    lw  v1,0(v0) 20751c: 1071fff4    beq v1,s1,2074f0 <_zn20qeventdispatcherunix6wakeupev+0x78> 207520: 8fbc0010    lw  gp,16(sp) 207524: 8fbf0030    lw  ra,48(sp) 207528: 8fb3002c    lw  s3,44(sp) 20752c: 8fb20028    lw  s2,40(sp) 207530: 8fb10024    lw  s1,36(sp) 207534: 8fb00020    lw  s0,32(sp) 207538: 03e00008    jr  ra 20753c: 27bd0038    addiu   sp,sp,56

the mips cpu doesn't have condition code register (an equivalent of x86 (e/r)flags register), if specify , code compiles, chances are, it's ignored. otoh, shouldn't have used in first place. wonder if "cc" has special meaning mips, far can't find anything. try removing "cc" , see if there's change in code or in behavior.

sigsegv means either code using bad pointer, or pointer isn't aligned (not multiple of 4).


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